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........ published in NEWSLETTER # 58

ADVANCES IN RAPID THERMAL AND INTEGRATED PROCESSING
by Dr. F. Roozeboom, Philips Research, Eindhoven (The Netherlands)

Today, ultra large scale integrated (ULSI) circuits are widely used in information technology, as well as design and manufacturing technology. The integrated circuits are currently designed to contain 64 Mbits per chip with 4-5 interconnect levels. During the past three decades chip complexity has roughly doubled every year, as a result of increasing chip size, reducing feature size and improvements in the device and circuit design. This is known as "Moore's annual doubling law". In this period the annual feature size shrinkage rate has been around 13%, the minimum feature size currently being 0.35 micrometer. At this rate in dynamic random access memory (DRAM) technology - which was and still is by far the most dominant high-volume technology - the Gbit-chip with 0-18 micrometer feature size, 4.5 nm gate oxide thickness and 5-6 interconnect levels will be in sight by the turn of the century.

Recently, the integrated circuit (IC) industries have been wondering how long Moore's law can be extrapolated while keeping wafer processing costs under control. The right choices in process and equipment technology will greatly affect the position of semiconductor industries in IC technology innovation. A trade-off between economic and technology factors has come into play to meet future roadmap needs. The most viable alternatives here are believed to be Rapid Thermal Processing and Integrated Processing, which allow minimization of processing and cycle times as well as a stringent ambient control. However, for this transition to take place, RTP must overcome current limitations in terms of temperature measurement and temperature uniformity control. Increasingly accurate temperature measurement is needed to avoid wafer-to-wafer variations and to provide heat source feedback- control, thus minimizing spatial temperature variations and, consequently, yield loss.

The purpose of the NATO Advanced Study Institute that produced this book was to advance the issues in single wafer thermal processing of microelectronic structures.

This book (NATO ASI SERIES E318) may be used as a guide to cope with the challenges faced by the microelectronics community. It contains 19 chapters and covers three inter-related areas: First, the "classical" area of photon-induced annealing of semiconductor and related materials, including fundamental pyrometry and emissivity issues and the modelling of reactor designs and processes, as well as their relation to temperature (non)-uniformity. Second is the area of process integration. Here the advances in basic equipment design, scale-up, integrated cluster tool equipment, including wafer cleaning and integrated processing, are treated. The third area is in the deposition and processing of thin films, epitaxial, dielectric and metal films. Selective deposition and epitaxy, integrated processing of layer stacks and new potential application areas such as in the processing of III-V semiconductor structures and thin film head processing for high-density magnetic data storage are included.
Reference books: B207, E47, E48, E62, E96, E136, E151, E318

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